“Therefore “zero bubble conditional branches” is not an exciting point. Existing CPUs from Intel, Arm, and AMD themselves can already handle conditional branches with zero bubbles.”
A YouTuber leaked AMD slides promising zero bubble branches, high accuracy prediction and a bigger BTB. Zen 3 already did zero bubble branching across 1,024 branches, and Intel’s Haswell did it before that. Calling branch prediction “high accuracy” is like an airliner advertising a pressurized cabin. The one real claim is a 48 KB, 12-way L1 data cache that holds at 4 cycles. Strip out the marketing and Zen 5’s slide has one new line on it.