“LLMs primarily pump out mediocre Verilog code.”
YC wants startups promising custom chips 5x to 100x faster from LLM-written hardware. High-level synthesis has made the same pitch since 1998, and it trades performance for designer productivity every time. Chip teams staff two verification engineers per designer because silicon bugs are expensive to fix. A tool that writes more mediocre Verilog faster gives those two engineers more to catch.