“Intel have actually sacrificed their flagship 512-bit instructions in order to run multiple threads in low-power cores.”
The P cores have AVX-512 in silicon and Intel switched it off, because the E cores don’t support it. Some boards found a way to turn it back on, and a microcode update killed that too, even on i3 chips with no E cores. DRM broke on the first design because the cores reported different CPUIDs. You paid for transistors Intel won’t let you use.